AREA EFFICIENT GF (p) ARCHITECTURES FOR GF (pm) MULTIPLIERS

This contribution describes new GF (p) multipliers, for p > 2, specially suited for GF (p) multiplication. We construct truth tables whose inputs are the bits of the multiplicand and multiplier and whose output are the bits that represent the modular product. However, contrary to previous approaches, we don’t represent the elements of GF (p) in the normal binary positional system. Rather, we choose a representation which minimizes the resulting Boolean function. We obtain improvements of upto 35% in area when compared to previous approaches for small odd prime £elds. We report transistor counts for all multipliers with p < 2 which we obtained through the SIS Sequential Circuit Synthesis program.